US$1.00-340.00
|
50 Pieces
(MOQ)
|
Basic Info.
Memory Card Application
Cell Phone
Quality
Genuine New Original
Specification
integrated circuit
Production Capacity
1000000PCS
Packaging & Delivery
Package Size
20.00cm * 20.00cm * 10.00cm
Package Gross Weight
1.000kg
Product Description
description W9812G6KH-6 : DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II
Mfr. Part#: W9812G6KH-6
Datasheet: (e-mail or chat us for PDF file)
ROHS Status:
Quality: 100% Original
Warranty: ONE YEAR
Type: | SDRAM |
Memory Size: | 128 Mbit |
Data Bus Width: | 16 bit |
Maximum Clock Frequency: | 166 MHz |
Package / Case: | TSOP-54 |
Organization: | 8 M x 16 |
Access Time: | 6 ns |
Supply Voltage - Min: | 3 V |
Supply Voltage - Max: | 3.6 V |
Minimum Operating Temperature: | 0 C |
Maximum Operating Temperature: | + 70 C |
Series: | W9812G6KH |
Packaging: | Tray |
Moisture Sensitive: | Yes |
Mounting Style: | SMD/SMT |
Product Type: | DRAM |
Factory Pack Quantity: | 108 |
Subcategory: | Memory & Data Storage |
Supply Current - Max: | 50 mA |
Unit Weight: | 1.304431 oz |
W9812G6KH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words x 4 banks x 16 bits. W9812G6KH delivers a data bandwidth of up to 200M words per second. To fully comply with the personal computer industrial standard, W9812G6KH is sorted into the following speed grades: -5, -5I, -5J, -6, -6I, -6J and -75. The -5/-5I grade parts are compliant to the 200MHz/CL3 specification (The -5I industrial grade which is guaranteed to support -40°C ≤ TA ≤ 85°C, the -5J industrial plus grade which is guaranteed to support -40°C ≤ TA ≤ 105°C). The -6/-6I grade parts are compliant to the 166MHz/CL3 specification (The -6I industrial grade which is guaranteed to support -40°C ≤ TA ≤ 85°C, the -6J industrial plus grade which is guaranteed to support -40°C ≤ TA ≤ 105°C). The -75 grade parts is compliant to the 133MHz/CL3 specification. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G6KH is ideal for main memory in high performance applications.
Certificates
Product Packing details
Why choosing us
Located in Shenzhen, the electronic market center of China. 100% guarantee components quality: Genuine Original. Sufficient stock on your urgent demand. Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing Faster shipment: In stock components can ship the same day . 24 Hours service
Notice:
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